Xilinx ISE

Last modified: 2020-01-31 13:17:04

Before we start

In the lab class we need to choose the configuration for the environment which allows us to use ISE.
The command for the environment choices is

cad
Select 0 -> Old legacy CAD versions
cad
To select ISE choose option 9.

Starting ISE

To start the program you must insert command

ise &

The & in the end of the command shows that the program is run in the backround and the
promt is returned immediately. It means that to run another process you don’t have
to open a new command line window. You can use & behind every process command.

ISE

Figure 1. ISE main view.

Creating a new project

In ISE you must create a new project. To do this follow the steps:

File->New Project.
Type in the name of the project.
Choose the location of the project.
A small description of the project wouldn’t hurt either.
Pick a suitable top-level source type: usually HDL.

ISE project naming

Figure 2. ISE new project dialog.

ISE needs a hardware platform linked to the project. Even though only a simulation is needed
this step cannot be ignored. The Institute has XESS Spartan3 FPGA’s which can be used as “dummy”
platforms. In case some other hardware platform is being used check for the correct
parameter values (package, speed etc.) from the vendor. So in this case we use:

Product Category: All
Family: Spartan 3E
Device: XC3S1200E
Package: FT320
Speed: -4
Synthesis Tool: XST(VHDL/Verilog)
Simulator: ISim(VHDL/Verilog)
Preferred Language: VHDL

The rest can be left as default.

ISE project properties title=

Figure 3. ISE new project specification.

After pressing Next the project summary window
shows once more all the chosen options. If everything seems to be correct press Finish.

Adding files to project

With the new project at hand we wish to add some files to the project. For instance
a testbech and an “empty” entity. To do this make a right click on the project file.
Select either New Source if you wish to write a new file or Add Source
if the file already exists somewhere.

To open the files double-click on them. If the Implementation radio buttons is chosen
then the component design file is opened. To see the testbench code choose the
Simulate radio button and then open the testbench file.

Adding files to a project

Figure 4. Adding files to a project.

Simulation

To simulate choose the Simulation radio button. It’s next to the Implementation.
In case of simulation we simulate the testbench. Make the testbench file active.
In the process tab ISim Simulator appears with two options:

Behavioral Check Syntax
Simulate Behavioral Model

Simulation

Figure 5. Starting simulation.

To simulate choose the latter. Also you can change the default simulation time by
doing a right click on the Simulate Behavioral Model option and choosing
Process Properties…. To change
the simulation time change the Simulation Run Time field value accordingly.

Simulation properties

Figure 6. Change simulation run time.

The ISE simulator has basically the same capabilities as the ModelSim one. You can
specify the simulation time, simulate step-by-step, restart simulator, change the
view of the simulation etc. To do all this check out the buttons and the menu options.

ISim simulator

Figure 7. Simulator view.

Change unchangeable radix

In case you cannot change the radix for a signal in the simulation waveform
you should follow the next instructions:

Select the unchangeable signal and another one, which you can change
Do a right click on the signal, which radix you can change
Choose the radix you would like to have for the unchangeable signal
Now the radix has changed for both selected signals
Change the radix back for the one you chose as the another signal

Synthesis

To synthesise a design choose the Implementation radio button.
Before making a synthesis you should add an UCF (User Constraint File) which
includes the pin assignments. NB! FPGA can be damaged without this!

To start the synthesis choose Generate Programming File. In this case
the ISE generates a .bit file which can be loaded to the FPGA (in case everything
is correct). To watch the created schematic open the Synthesize-XST menu
and pick the View RTL Schematic option.